In the course of the advancing digitalization in signal processing and the transmission of electrical signals, which are available in analog form at the beginning, faster and faster analog/digital converters are required. Pipelined ADCs, which have been known for several years, are a well-known architecture for this, with their high conversion rate and justifiable technical circuit complexity and thus a small chip area. However, this arrangement at the block diagram level is not optimal in the sequence of time.